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https://anycpu.org/forum/viewtopic.php?f=23&t=978 "DIP-8: 8-bit TTL computer"

https://github.com/jimjag/JJ65c02

http://axio.ms//projects/2024/06/16/MicroMac.html

https://www.google.com/search?q=NEO6502

https://retrogamecoders.com/neo6502-review/

https://retrogamecoders.com/wp-content/uploads/2024/02/Screenshot-by-Dropbox-Capture-2.png

https://github.com/OLIMEX/Neo6502/blob/main/HARDWARE/Neo6502-rev-B1/Neo6502_Rev_B1.pdf

https://www.makerhacks.com/z80-io-lcd/

https://damieng.com/typography/zx-origins/

https://hackaday.com/2023/08/07/all-about-usb-c-example-circuits/

https://www.digikey.com/en/products/detail/adafruit-industries-llc/1833/5629431?

https://github.com/JayesonLS/TandyCircuitsAndLogic/tree/master

https://www.nexperia.com/products/analog-logic-ics/logic/family/LVC/#/p=1,s=0,f=,c=,rpp=,fs=0,sc=,so=,es=

74LVC245A-Q100;
74LVCH245A-Q100
Octal bus transceiver; 3-state

The 74LVC245A-Q100; 74LVCH245A-Q100 is an 8-bit transceiver with 3-state outputs. The device features an output enable (OE) and send/receive (DIR) for direction control. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

74LVC273
Octal D-type flip-flop with reset; positive-edge trigger

The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

74LVC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs;
positive-edge trigger; 3-state

The 74LVC374A is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

74LVC138A
3-to-8 line decoder/demultiplexer; inverting

The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the 74LVC138A to a 1-of-32 (5 to 32 lines) decoder with just four 74LVC138A ICs and one inverter. The 74LVC138A can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

74LVC4066-Q100
Quad bilateral switch

The 74LVC4066-Q100 is a high-speed Si-gate CMOS device.

The 74LVC4066-Q100 provides four single pole, single-throw analog switch functions. Each switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE). When nE is LOW, the analog switch is turned off.

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